This technology relates to a semiconductor device, and more particularly to a semiconductor device which has a structure including a through-electrode provided therein and stacked in a stacked semiconductor apparatus and a stacked semiconductor apparatus configured by stacking such semiconductor devices.
As an integrated semiconductor apparatus including a plurality of semiconductor chips, a stacked semiconductor apparatus in which semiconductor chips are stacked is known. In the stacked semiconductor device, the mounting area for the semiconductor chips can be reduced significantly, for example, in comparison with an integrated semiconductor apparatus wherein semiconductor chips are arranged in a plane.
Further, in the stacked semiconductor apparatus, it has been proposed to form a through-electrode called TSV (Through-Silicon Via) in semiconductor chips, and is being developed to achieve practical implementation thereof.
By forming through-electrodes in semiconductor chips, it becomes possible to lay wiring lines between the chips by connections of the through-electrodes to each other in a stacked semiconductor apparatus. This eliminates the necessity for connection by wire bonding.
According to wiring bonding, since a wiring line must be led out from an end portion of a semiconductor chip, the number of connections between semiconductor chips is limited to approximately 100 to 200. In contrast, in the case of through-electrodes, it is possible to form them at distances of, for example, several tens μm in a semiconductor chip. Therefore, it is possible to easily form more than 1,000 through-electrodes in one semiconductor chip. Consequently, also it is possible to increase the number of connections to a different semiconductor chip to 1,000 or more.
In order to manufacture a stacked semiconductor apparatus which includes such through-electrodes as described above, it is necessary to test connections between through-electrodes in regard to whether or not they are good. A boundary scan method is known as one of techniques for testing whether or not a connection between semiconductor chips is good. The boundary scan method is standardized as IEEE Standard 1149.1 Standard Test Access Port and Boundary-Scan Architecture. This boundary scan standard has been standardized by JTAG (Joint Test Action Group).
In a test according to the boundary scan, an internal circuit ready for boundary scan is incorporated in advance in a semiconductor chip which makes an object of the test. The internal circuit is also called boundary scan cell and is provided, for example, corresponding to each of terminals for connecting the semiconductor chip to an external circuit. Then, the boundary scan cell is controlled to input or output a signal from or to the external circuit while such semiconductor chips are connected to each other by a daisy chain thereby to decide whether or not the connections between the semiconductor devices are good.
Also such a related art as described below is known as a connection test between semiconductor chips of a stacked semiconductor apparatus. In particular, a diode element for a conduction check is connected at the cathode thereof to each of an internal terminal, that is, a through-electrode, in each semiconductor chip. Further, an external terminal connected commonly to the anode of the diodes in one semiconductor chip is provided on each of the semiconductor chips of different layers. Further, a terminal for exclusive use for a conduction test is provided for each of wiring lines of the through-electrodes which are connected to each other between the semiconductor chips. Then, a predetermined voltage is applied to a combination of each one of the external terminals and each one of the terminals for exclusive use for a conduction test to select and drive one diode element. The value of current flowing through the diode element driven in this manner is measured to decide the connection state of the through-electrodes corresponding to the diode element (refer to Japanese Patent Laid-Open No. 2009-139273, particularly FIG. 1).